Description
This report analyzes the technology for flip chip technology and WLPs, presenting forecasts for packages by type and application.
Advanced wafer-level packaging technologies hold the key to meeting future technology needs, from mobile devices to automotive applications, to those required for enabling the IoT. Flip chip technology is slowly replacing wire bonding for many high-performance chips. Flip Chip (FC) is not a specific package (like SOIC), or even a package type (like BGA). Flip Chip describes the method of electrically connecting the die to the package carrier whereby the interconnection between the die and carrier is made through a conductive “bump” or copper pillar that is placed directly on the die surface. The bumped die is then “flipped over” and placed face down, with the bumps connecting to the carrier directly.
This technology can be applied on application processor, baseband, PMIC, memory devices, etc. products. For mobile communications, flip chip development is driven by increased device performance and package miniaturization trends, particularly for the CPU or so called applications processor that powers smart phones and media tablets.
To meet the needs of thinner mobile devices, Wafer Level Packages (WLPs) have been developed. They differ from flip-chip packages primarily in that the die is mounted directly on the PCB. The reduced form factor provided by mounting the die directly on the PCB has vaulted WLP to the leading position for smartphones and other products where space is at a premium.
Flip chips are appearing in a plethora of high-volume consumer products such as mobile phones, digital cameras, MP3 players, and computer peripherals. This report examines the market for flip chip ICs by device application, and the lithography and wet etch tools used in their manufacture.
Flip Chip/WLP Manufacturing and Market Analysis
TABLE OF CONTENTS
Chapter 1. Introduction
Chapter 2. Executive Summary
Chapter 3. Flip Chip/WLP Issues and Trends
3.1. Introduction
3.2. Wafer Bumping
3.2.1. Solder Bumps
3.2.1.1 Metallurgy
3.2.1.2 Deposition Of UBM
3.2.1.3 Sputter Etching
3.2.1.4 Photolithography
3.2.1.5 Solder Deposition
3.2.1.6 Resist Strip
3.2.1.7 UBM Wet Etch
3.2.1.8 Reflow
3.2.1.9 Flux Issues
3.2.2. Gold Bumps
3.2.2.1 Bump Processing
3.2.2.2 Bonding
3.2.2.3 Coplanarity
3.2.2.4 Conductivity
3.2.2.5 Thermal Properties
3.2.2.6 Size
3.2.2.7 Reliability
3.2.2.8 Cost Issues
3.2.3. Copper Pillar Bumps
3.2.4. Copper Stud Bumping
3.2.5. C4NP
3.3. Wafer Level Packaging
3.4. Pad Redistribution
3.5. Wafer Bumping Costs
3.5.1. Wafer Redistribution And Wafer Bumping Costs
3.5.2. WLCSP Hidden Costs
3.5.3. WLCSP Cost Per Good Die
3.5.4. Wafer-Level Underfill Costs
3.6. Panel Level Packaging
Chapter 4. Lithography Issues And Trends
4.1. Issues
4.1.1. Technical Performance
4.1.2. Capital Investment
4.1.3. Cost Of Consumables
4.1.4. Throughput
4.1.5. Ease Of Use
4.1.6. Flexibility
4.1.7. Equipment Support
4.1.8. Resolution
4.1.9. Solder Bumping Capabilities
4.1.10. Gold Bumping Capabilities
4.2. Exposure Systems
4.2.1. Introduction
4.2.1.1 Reduction Steppers. 4.
4.2.1.2 Full-Field Projection
4.2.1.3 Mask Aligners
4.2.1.4 1X Steppers
4.2.1.5 2X Steppers
4.3. Competitive Technologies
4.3.1. Inkjet Printing
4.3.2. Stencil/Screen Printing
4.3.3. Electroless Metal Deposition
Chapter 5. UBM Etch Issues And Trends
5.1. Introduction
5.2. Technology Issues And Trends
5.2.1. Process Flow
5.2.2. Etch Process
5.2.3. Etch Chemistry
5.3 Batch Versus Single-Wafer Etching
Chapter 6. Metallization Issues and Trends
6.1. Introduction
6.2. Sputtering Metallization
6.2.1. Gold Bump
6.2.2. Solder Bumping
6.2.2.1 T i / Cu and TiW / Cu
6.2.2.2 Al / NiV / Cu
6.2.2.3 T i / N i (V) and TiW / Ni ( V )
6.2.2.4 Cr / Cr-Cu / Cu
6.2.3. Copper Bumping
6.3. Electrodeposition
Chapter 7. Market Analysis
7.1. Market Drivers For Flip Chip And WLP
7.2. Market Opportunities
7.3. Challenges
7.4. Flip Chip Market
7.4.1. Market Dynamics
7.4.2. Market Forecast
7.5. Lithography Market
7.5.1. Introduction
7.5.2. Market Analysis
7.6. Deposition Market
TABLES
3.1. Common UBM Stacks For Solder And Gold Bumping
3.2. Solder Bumping Guidelines
3.3. Gold Bumping Guidelines
3.4. Copper Bumping Guidelines
3.5. Comparison Of Solder Bumping Processes
3.6. ITRS Pin Counts For Different Applications
3.7. Pillar-WLP CSP Guidelines
3.8. Pad Redistribution Guidelines
3.9. Panel Level Packaging Roadmaps
4.1. Key Challenges For WLP Lithography
4.2. Lithography Tools By Vendor
5.1. UBM Film Etchants
5.2. Advantages Of Spin Processing
6.1. Common UBM Stacks For Gold And Solder Bumping
7.1. WLP Demand by Device (Units)
7.2. WLP Demand by Device (Wafers)
7.3. Worldwide Lithography Forecast
7.4. Worldwide Forecast For Deposition Tools
FIGURES
3.1. C4 Chip Connections
3.2. Wafer Bump Technology Roadmap
3.3. Comparison Of Copper Pillar, Flip Chip, And WLP
3.4. Solder Bumping Process
3.5. Three Process Flows For Solder Bumping
3.6. Gold Bumping Process
3.7. Cost Per Gold Bumped Wafer
3.8. Copper Stud Bump
3.9. Breakdown Of Stud Bumping Costs
3.10. C4NP Process Description
3.11. Pillar-WLPCSP Process
3.12. Illustration of Stacked FOWLP
3.13. FOWLP Process Flow Options
3.14. Pad Redistribution Process
3.15. Number of Die on Panel
4.1. Laser-Projection Imaging
4.2. Solder Jet Technology
4.3. Principle Of Screen Printing
4.4. Principle Of Inkjet Printing
4.5. Electroless Under Bump Metallization
5.1. Electroplated Solder Bumping Process
6.1. Indium Bump For Focal Plane Arrays
6.2. Indium Bump For FPA Today And Tomorrow
7.1. WLP Applications
7.2. Wire Bond versus Flip Chip
7.3. Flip Chip and Wire Bond Equipment Forecast
7.4. Growth in Copper Wire Bonding
7.5. Flip Chip Market By Number Of Devices
7.6. Flip Chip Market By Number Of Wafers
7.7. WLP Market by Device – 2016
7.8. WLP Market by Device – 2022
7.9. Device Shipment Forecast WLP Vs Flip Chip
7.10. Device Shipment Forecast FIWLP Vs FOWLP
7.11. Historic Lithography Market Shares
7.12. Lithography Market Share Growth
7.13. ECD Market Shares
7.14. Sputtering Market Shares
