Description
The explosion of applications in the consumer and mobile space, internet of things (IoT) and the slowdown of Moore’s law have been driving many new trends and innovations in packaging. The semiconductor industry now has to focus on system scaling and integration to meet the ever-increasing electronic system demands for performance and functionality, and for reduction of system form factor, system power consumption and system cost. This paradigm shift from chip-scaling to system-scaling will re-invent microelectronics, continue driving system bandwidth and performance, and help sustain Moore’s Law. The challenge for semiconductor industry is to develop a disruptive packaging technology platform capable of achieving these goals.
This report discusses the packaging trends for higher performance and density driving advanced packaging technology solutions for mobile and IoT applications. One of the key enabling technologies to achieve these goals is thin 3D-packaging with integration. Developments have lately been made with various embedding technologies, such as eWLB/Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D IC´s (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.
High-density packages have been subcategorized to better define their content and function.
An MCM is described as a package combining multiple IC’s into a single system-level unit. The resulting module is capable of handling an entire function. These MCM packages typically have custom pin out configurations as well.
MCP, or multi-chip packages (sometimes referred to as few chip packages), are typically low lead count combinations of simple IC’s. For these packages system control still occurs at the board level. They are primarily produced in volume in standard pin out and package configurations such as DIPs SOJs, QFPs and BGAs.
System-in-Package (SIP) is much more than an IC package containing multiple die. SIP products are fully functional systems or sub-systems in an IC package format. SIP may contain one or more IC chips (wirebonded or flip chip) plus other components that are traditionally found on the system mother board.
The increasing complexity and integration of electronic systems require advanced packaging and multichip module (MCM) techniques.
Various types of multichip packages (MCPs) have been used for many years, but costs have always kept volumes relatively low. Now, however, the felicitous combination of SRAM and flash memory chips in a single package for cell-phone applications is finally creating a high-growth, high-volume market for the multichip packaging.
Multichip packages hold high growth potential, but confusion with MCM technology makes exact forecasting difficult. Regardless of nomenclature, the forecasts offer proof that, by offering high performance in miniaturized spaces, MCPs make an attractive solution for next-generation wireless applications, primarily in mobile phones, but are also likely to become commonplace in various notebook computing applications.
SIP is basically an MCM, but it provides higher density and better time-to-market than the older MCM technology. While MCMs excel in reusability and flexibility, and SoCs excel at performance and density, the SIP is a compromise between the two. Testability and yield are the key deciding factors in the choice between SoC and SIP.
SIP technology is an ideal solution in markets that demand smaller size with increased functionality. However, SIP has the added benefit of compatibility with die design changes and integration of various die technologies (e.g., Si, GaAs, SiGe, SOI, MEMS and Optical) without the high cost and lead time associated with SoC development and manufacturing.
High-Density Packaging (MCM, MCP, SIP, 3D-TSV): Market Analysis and Technology Trends
TABLE OF CONTENTS
Chapter 1 Introduction
Chapter 2 Executive Summary
2.1 Summary of Technology Issues
2.2 Summary of Market Forecasts
Chapter 3 Technology Issues and Trends
3.1 Overview of HDP Technology
3.1.1 Need for Multiple IC Integration
3.1.2 Challenges of Multiple IC Integration
3.2 Technical Constraints of Integration
3.3 Economic Benefits of HDP
3.4 Technology Issues
3.4.1 Substrates
3.4.2 Conductors
3.4.3 Dielectrics
3.4.4 Vias
3.4.5 Die Attachment
3.4.6 Next Level Interconnection
3.4.7 Thermal Management
3.4.8 Test and Inspection
3.4.9 Design
3.5 3-D Modules
3.6 Superconducting Interconnects
3.7 Known Good Die
3.8 System In Package (SIP)
3.9 Multichip Package
3.10 Package-On-Package (PoP)
Chapter 4 Applications
4.1 Semiconductor Industry by End Market
4.1.1 Application Processors
4.1.2 Microprocessors
4.1.3 Programmable Logic Devices (PLDs)
4.1.4 Analog Devices
4.1.5 DRAM and NAND
4.2 Semiconductor Industry by End Market
4.2.1 Military and Aerospace
4.2.2 Computer and Peripheral Equipment
4.2.3 Communications
4.2.4 Consumer
4.2.5 Industrial
Chapter 5 Competitive Environment
5.1 Overview of the HDP Competitive Environment
5.2 Joint Ventures and Cooperative Agreements
5.3 HDP Manufacturers
Chapter 6 3-D-TSV Technology
6.1 Driving Forces In 3D-TSV
6.2 3-D Package Varieties
6.3 TSV Processes
6.4 Critical Processing Technologies
6.4.1 Plasma Etch Technology
6.4.2 Cu Plating
6.4.3 Thin Wafer Bondling
6.4.4 Wafer Thinning/CMP
6.4.5 Lithography
6.5 Applications
6.6 Limitations Of 3-DPackaging Technology
6.6.1 Thermal Management
6.6.2 Cost
6.6.3 Design Complexity
6.6.4 Time To Delivery
6.7 Company Profiles
Chapter 7 Market Forecast
7.1 Overview of Multichip Modules
7.2 Driving Forces
7.3 System-in-Package (SiP)
7.4 Flip Chip/Wafer Level Packaging
7.5 Worldwide IC Market Forecast
7.6 Worldwide Packaging Market Forecast
7.7 Worldwide MCM Market Forecast
7.7.1 Worldwide Forecast By Substrate Type
7.7.2 Worldwide 3-D Through Silicon Via (TSV) Market
List of Tables
3.1 Multichip Modules Vs. Circuit Board Assemblies
3.2 MCM Cost Comparison
3.3 Substrate Technology Features
3.4 Metal Conductors in MCMs
3.5 Comparison of Thin-Film and Thick-Film Technologies
3.6 Characteristics of Dielectric Materials
3.7 CTE of Common Substrates and Adhesives
3.8 Density Comparisons of Single Package and 3-D MCM
4.1 DRAM Supply Forecasts
4.2 DRAM Demand Forecasts
4.3 DRAM Demand Forecasts
4.4 NAND Supply Forecasts
4.5 NAND Demand Forecasts
4.6 NAND Demand Forecasts
4.7 PC Unit Shipment Forecast, 2011-2014
5.1 MCM Manufacturers
6.1 3-D Mass Memory Volume Comparison Between Other Technologies and TI’s 3D Technology In Cm3/Gbit
6.2 3-D Mass Memory Weight Comparison Between Other Technologies and TI’s 3D Technology In Grams3/Gbit
7.1 Worldwide IC Package Market Forecast
7.2 Worldwide MCM Market
List of Figures
1.1 Schematic Cross-Section View Of An MCM-D
1.2 Cross-Section Of The RF And Microwave MCM-D Structure
1.3 Thin Film Layers On The Planarized Core Layer Of MCM-SL/D Technology
1.4 Flip Chip MCP
1.5 SIP Cross Section
3.1 IC Packaging Trends
3.2 Technology Tree For HDP Types
3.3 Form Factor Decrease By Package Type
3.4 High Power Package Technology Roadmap
3.5 Comparison Between Wire Bonding And Bump
4.1 PoP 3chipstack Package
4.2 Application Processor Revenue
4.3 MPU Unit Shipments And Growth Trends
4.4 ASIC and ASSP Design Starts
4.5 PLD Share of Revenue by End Market
4.6 Analog IC Revenue
4.7 FCFBGA Memory Package
4.8 FBGA 2-Chip Memory Package
4.9 FBGA QDP Memory Package
4.10 Semiconductor Unit Demand By End Market
4.11 Military and Aerospace Semiconductor Revenue
4.12 Server shipments
4.13 Wireless semi revenue
4.14 Silicon Content Of Mobile Phones
4.15 Consumer Semi Revenue
4.16 Average Semi Content By Application
4.17 Automotive Semiconductor Revenue
4.18 Industrial Semiconductor Revenue
6.1 3-D Technology On DRAM Density
6.2 3-D Through-Silicon Via (TSV)
6.3 Graphical Illustration Of The Silicon Efficiency Between MCMs And 3D Technology
6.4 Silicon Efficiency Comparison Between 3D Packaging Technology And Other Conventional Packaging Technologies
6.5 3D Packages
6.6 Via First, Middle, And Last Process Flows
6.7 Via First TSV Process Flow
6.8 New Applications Driving TSV Growth
6.9 Projection Of TSV Applications And Process Requirements
6-10 3-D Technology For DRAM
6.11 Moore’s Law For Active Element Density
7.1 Various System-In-Package (SiP) Applications
7.2 SiP Structures
7.3 Wire Bond Versus Flip Chip
7.4 Flip Chip And Wire Bond Equipment Forecast
7.5 Growth In Copper Wire Bonding
7.6 WLP Demand By Devices
7.7 WLP Demand By Wafers
7.8 Projection of 3-D TSV Applications And Process Requirement
7.9 Market Forecast of 3-D TSV Wafers
7.10 Market Forecast of 3-D TSV Wafers
